R&D Experience

Embedded Systems (EMBED) Track

Week 1 - Theory Module

EMBED Team: Yuri Cauwerts, Songqiao Cui

Academic Year 2024-2025
Campus Groep T - KU Leuven

Menu for the day

Theory session

Part 1 | Verilog Recap

Verilog HDL

Describe

We can express digital logic elements and circuits
(NOT, AND, adder, flip-flop, memory, etc.)

Simulate

We can validate the functional specification under certain input stimuli

filename: AND_gate.v

 

  1. Module Identifier

filename: AND_gate.v

 

  1. Module Identifier

  2. Module Declaration

filename: AND_gate.v

 

  1. Module Identifier

  2. Module Declaration

  3. Module Architecture

filename: AND_gate.v

 

  1. Module Identifier

  2. Module Declaration


  3. Module Architecture

filename: AND_gate.v

 

filename: AND_gate.v

 

  1. Module Identifier

  2. Module Declaration


  3. Module Architecture

In this example: simple continous assignment

Wire vs. Reg

  • The data type of a port can be either wire or reg
  • Both are by default 1-bit data types and accept 4 values:

    0Logic zero
    1Logic one
    ZLogic High impedance
    XUndefined value

  • Important: wire and reg are different types in Verilog
    • A wire is always a node (connection to transfer logic signals inside the circuit)
    • A reg can be a node or a flip-flop
  • Depends on how we declare the always block (more later)

Logic Gates

Boolean (or bitwise)
operators in Verilog:

Verilog symbolDescription
~Bitwise NOT
&Bitwise AND
|Bitwise OR
^Bitwise XOR

Multi-bit Variables

  • By default, wire and reg types are 1-bit variables
  • We can extend them to N-bits with
    wire[N-1:0] or reg[N-1:0]
  • Convention:
    • N-1 indicates MSB (Most Significant Bit)
    • 0 indicates LSB (Least Significant Bit)
     
  • Concatenation (very useful in HW/SW co-design to get data inputs into a register)

Boolean Equations

Boolean Equation

$Y = A . C + B . \bar C $

1A. Simple continuous assignments

  • Compact way -> single assignment
    • Beware of order precedence!
    • Higher precedence : NOT (~)
    • Lower precedence : AND (&) and OR(|)

  • Readable way -> several assignments
    • Declare local variables (of type wire)
    • Where? Right after module declaration
    • Break equation into assignments

Both codes translate to the exact same circuit:

Verilog - Equality, Logical and Relational Operators

Equality operators

Verilog symbolDescription
==Equal to
!=Not equal to

Relational operators

Verilog symbolDescription
>Greater than
<Less than
>=Greater than or equal to
<=Less than or equal to

Logical operators

Verilog symbolDescription
!Logical negation
&&Logical AND
||Logical OR

Verilog - Expressing Behaviour

Behaviour

When C=1 then Y=A
When C=0 then Y=B

1B. Conditional continous assignments

  • In Elaborated Design, this code translates to:

    which is a more compact and intuitive visualization
    than the previous code:

  • Important! Both codes are completely equivalent!!!

  • Internally, a MUX requires the same logic gates

Verilog - Structural Design

Structural Design

  • Validation with Elaborated Design
  • Note: Structural design is rarely used to instantiate basic logic gates (as in this example)
  • But it is very useful for larger circuits, in order to obtain a modular design

Verilog - Always Block

  • To facilitate system modeling, Verilog contains a primitive called always block
  • An always block allows to group multiple procedural assignment together
  • Syntax:
  • There are 2 types of always block in Verilog:
    1. Combinational always block: allows to describe combinational circuits
    2. Clocked always block: allows to describe storage elements such as flip-flops

Verilog - Always Block

  • IF Statement
  • CASE Statement

Verilog - Combinational Always Block

combinational always block
basic example
  1. The first line will always be always @ (*)
  2. We use what is called a blocking assignment using =
  3. Inside an always block, the object [variable_name] must be of type reg
  4. Objects in [expression] can be either of type reg or type wire

Verilog - Combinational Always Block (Examples)

Boolean Equation

$Y = A . C + B . \bar C $

Example #1
Example #2
Behaviour


When C=1 then Y=A
When C=0 then Y=B

Verilog - Clocked Always Block

clocked always block
basic example
  1. The first line will always be always @ ( posedge iClk)
  2. We use what is called a non-blocking assignment using <=
  3. Inside an always block, the object [variable_name] must be of type reg
  4. Objects in [expression] can be either of type reg or type wire

Verilog - Combinational vs Clocked Always Block

Combinational Always Block
Elaborated design:
Clocked Always Block
Elaborated design:

Verilog - D-type Flip-Flop



Behavioural diagram
Behavioural diagram

Verilog - Registers and Shift Registers

Verilog - Counters

Verilog - Finite State Machines (Moore)

  1. State Register (sequential) : used to store and hold the current state of the machine
    At each rising edge of the clock, it updates the current state with the value of the next state.

  2. Next State Logic (combinational) : determines the value of the next state
    Calculations based on inputs and current state, e.g. next state = f(inputs, current state)

  3. Output Logic (combinational) : determines the value of the outputs
    Calculations based only on current state, e.g. output = f(current state)

Verilog - Testbenches (combinational)

Verilog - Good Practices

  • You should always use descriptive identifiers: what does the signal do?

  • Use prefixes to differentiate between objects

    • Input ports: iOp1, iOp2, iClk, iRst, iEn, etc.
    • Output ports: oRes, oEn, oValid, oReady, etc.
    • Local vars of type wire: w1, wTmp, wNext, etc.
    • Local vars of type reg: rState, rCounter, etc.
    • Parameters (uppercase): WIDTH, BIT_LENGTH, CLKS_PER_PERIOD, etc.

  • Use suffixes in identifiers to represent special characteristics:
    • Example: iRst_n (to indicate the signal is active-low)

Part 2 | Debugging

Part 3 | Zynq Architecture

Part 4 | Boot Procedure

The Lorenz Equations

  • Part 4: Communication Protocols
  • Part 5: AXI
  • Part 6: Interrupts / Polling

\[\begin{aligned} \dot{x} & = \sigma(y-x) \\ \dot{y} & = \rho x - y - xz \\ \dot{z} & = -\beta z + xy \end{aligned} \] When \(a \ne 0\), there are two solutions to \(ax^2 + bx + c = 0\) and they are $x = \dfrac{-b \pm \sqrt{b^2-4ac}}{2a}.$

PlantUML

						
						  @startuml
						  skinparam sequenceArrowThickness 5
						  Alice -> Bob: Authentication Request
						  Bob --> Alice: Authentication Response
						  Alice -> Bob: Another authentication Request
						  Bob --> Alice: Another authentication Response
						  @enduml