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Zynq

A System-on-a-Chip (SoC) is an integrated circuit that combines multple components of a computer system onto a single chip. Zynq is an All-Programmable System-on-Chip. It combines a dual-core ARM Cortex-A9 processor with traditional FPGA logic fabric. The ARM Cortex-A9 is an application grade processor, capable of running a full operating system, such as Linux. The programmable logic is based on the Xilinx 7-series FPGA architecture.

Have a look at the overview of AMD Zynq 7000 SoCs.

This architecture uses the standard AXI interfaces, which provide high bandwith, low latency connections between the Processing System (PS) and the Programmable Logic (PL). We will have a detailed look at AXI a bit further in this course.

The benefits of using a SoC are:

  • lower cost
  • faster and more secure data transfers between the various system elements
  • higher overall system speed
  • lower power consumption
  • smaller physical size
  • better reliability

The PS has a fixed architecture and hosts the processor and system memory, the PL is completely flexible, giving the designer a 'blank canvas' to create custom peripherals or to reuse the standard ones. The interconnections are implemented via AXI interfaces linking the PS and PL.

Design Reuse

Until now we have been using IP blocks from Xilinx. In Vivado it is possible to create IP blocks from our design. When we develop peripherals as IP blocks in Vivado, we can reuse them in different projects. Or we can use IP blocks written by third parties or open source repositories. There is no need to reinvent the wheel. Reusing components is ok. But it is important to understand how those components work.

That is why we will see some standard communication protocols that could be implemented in IP blocks. After that we will see how IP blocks can interact with eachother using an industry defined standard, AXI interfaces.

Design Flow

Zynq PS Detail

The Application Processing Unit (APU) has two ARM processing cores, each having a NEON Media Processing Engine (MPE) and Floating Point Unit (FPU); a Memory Management Unit (MMU); Level 1 Cache memory (Instruction and Data); Level 2 cache; On Chip Memory and a Snoop Control Unit (SCU) that forms a bridge between the ARM cores and the Level 2 cach and OCM memories, this SCU also is responsible for interfacing with the PL via the Accelerator Coherency Port (ACP). The role of the MMU is to translate between virtual and physical addresses, which we will see later in this course. Timers and Interrupt Controllers (GIC) are also present in the APU.

Vitis (in the book still reffered to as Xilinx SDK) is the application we use to write applications that can run on the PS.

PS to External Interfaces

The communication between PS and the outside world is achieved primarily via the Multiplexed Input/Output (MIO). This provides 54 pins of flexible connectivity. Certain connections can be made via the Extended MIO (EMIO), this is not a direct path from the PS to external connections, but instead passes through and shares the I/O resources of the PL. EMIO can be used when more then 54 pins are required or as a method of interfacing between the PS and an IP block implemented in the PL.

The MIO includes standard communications interfaces (SPI, I2C, CAN, UART, SD, USB, GigE) and General Purpose Input/Output (GPIO) which can be used for simple buttons, switches, LEDs, ... .

PL - The Logic Fabric

See the Zynq Book p23-25 for a detailed explanation of these elements.

DSP48E1s and Block RAMs

In addition to the general fabric there are two special purpose components.

  • Block RAM for dense memory requirements
  • DSP48E1 slices for high speed arithmetic

Both are embedded into the logic fabric and are located in proximity to each other due to optimisation (green and blue blocks on the presentation of the Logic Fabric above).

Each Block RAM can store up to 36Kb of information. The shape of the memory can be configured (eg. 18 bits x 2048, 1 word = 18 bits or 8192 x 4 bits). Block RAM can be combined to form larger memory capacity.

Distributed RAM is created using LUTs. For large memories this would lead to poor performance due to increased logic and routing delays. It is often advantageous to implement small memories using distributed RAM. Vivado will optimize the usage of logic fabric when creating memories, just as it does for arithmetic operations (LUTs vs DPSs).

GPIO

The IOBs on the Zynq are referred to as SelctIO Resoures, these are organised into banks of 50 IOBs each. Each IOB contains one pad which provides the physical connection to the outside world for a single input or output signal.

XADC

WARNING: Voltage Limit!

Be careful when using this interface, there are maximum voltages that the XADC can handle. Read more about the XADC in the references.

The XADC is a dedicated hard IP component on the PL, which feature two separate 12-bit ADCs capable of sampling external analogue input signals at 1Msps. Control is achieved using the PS-XADC inteface block located within the PS.